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Resampling DAC to avoid jitter
post Jul 20 2002, 16:09
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Originally posted by Wombat
I have a DAC here around that claims to
be jitter-free.

They "resample" the whole incoming signal to a new stream.

Can somebody explain?

A view in the service manual shows that the incoming signal is send to a to a dsp -> 
sdram -> sample rate converter -> d/a part with the clock crosslinked to incoming clock with a sampling rate counter and flame counter.

I don't understand how this could improve the sound !

If I'm guessing right, it should work like this. Let's consider the original digital signal, in blue, with its time code, in red:

Now, say that passing through SPDIF, it suffers from jtter. Here's how it comes into the DAC :

As far as I understand Asynchronous sample rate conversion, it oversamples the incoming signal, here, I drew 4 times :

Then it resamples it to a new clock, taking the nearest sample on demand from the oversampled signal :

Okay ! That's right, the result is jitter free rolleyes.gif ! The time code is perfectly even and does not suffer from the jitter coming from the SPDIF, that's what we wanted, no ?

Now, what about improving the sound ?
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post Jul 26 2002, 00:20
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most important seems this FIFO Buffering

"...it is evident that a sample rate converter must possess
some sort of an elastic sample buffer"

This is a link a friend gave me for "easy understanding" tongue.gif

Sorry i don´t get it for explanation ???

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