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Resampling DAC to avoid jitter
Pio2001
post Jul 20 2002, 16:09
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QUOTE
Originally posted by Wombat
I have a DAC here around that claims to
be jitter-free.

They "resample" the whole incoming signal to a new stream.

Can somebody explain?

A view in the service manual shows that the incoming signal is send to a to a dsp -> 
sdram -> sample rate converter -> d/a part with the clock crosslinked to incoming clock with a sampling rate counter and flame counter.


I don't understand how this could improve the sound !

If I'm guessing right, it should work like this. Let's consider the original digital signal, in blue, with its time code, in red:



Now, say that passing through SPDIF, it suffers from jtter. Here's how it comes into the DAC :



As far as I understand Asynchronous sample rate conversion, it oversamples the incoming signal, here, I drew 4 times :



Then it resamples it to a new clock, taking the nearest sample on demand from the oversampled signal :



Okay ! That's right, the result is jitter free rolleyes.gif ! The time code is perfectly even and does not suffer from the jitter coming from the SPDIF, that's what we wanted, no ?

Now, what about improving the sound ?
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Wombat
post Jul 20 2002, 16:29
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Well i don´t know?

The sampling rate converter uses a decimation filter
and oversampling retaining 20 bit accuracy for time and level.

What this means - ?

I Emailed somebody who should know it correctly, as soon
i know something i´ll be back!

regards

Wombat
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Pio2001
post Jul 20 2002, 18:39
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All I could understand, and I hope I'm wrong because it's an unuseful process, is that the incoming stream is resampled to a jitter free clock. But doing this, this should record the jiter distortion of the incoming stream forever in the output digital data. Therefore no quality gain.
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godzilla525
post Jul 22 2002, 16:15
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If you sync a low-jitter PLL to the incoming signal, wouldn't that solve the problem? Wouldn't using a PLL result in more of a "low-pass resonant circuit" that effectively takes the sum of the jitter from a bunch of consecutive pulses, essentially nulling it out?

Maybe it would take some high-speed digital processing to determine the sum of all the jitter and find the average?

Just some crackpot ideas. biggrin.gif


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KikeG
post Jul 22 2002, 16:28
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Yes, resampling the signal is no good. The best solution is syncing to the incoming signal, and recover the signal clock using a good PLL circuit that produces a low jitter output. The best solution would be reclocking, but I'd say this is a bit more complicated to achieve.
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Wombat
post Jul 25 2002, 19:33
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Hello!

"Asynchronous Sample Rate Converter" works different

The shematics above is a kind of reclocking against.

An explanation of a chip of Analog Devices that uses
the same technics can be found here:

http://www.analog.com/library/techArticles...ers/AD1890.html

A newer models short description:

http://www-personal.engin.umich.edu/~jglet...lcyon/asrc.html



btw. mine is clocked at 49.152MHz -> resampling to 96kHz



Wombat
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Pio2001
post Jul 26 2002, 00:01
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It's very difficult to understand their explanations, but if I understod well, they lock the SRC process to a given ratio (by lowpassing the ratio detector), eliminating jitter, because contrary to what my pictures show, the samples are not taken on demand, but given by the SRC ratio, and when the clocks drift, they slowly change the SRC ratio to follow.
In other words, the SRC ratio behaviour is just lowpassed at 3 Hz.

Is it it, or am I completely confused ?
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Wombat
post Jul 26 2002, 00:20
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Well,

most important seems this FIFO Buffering

"...it is evident that a sample rate converter must possess
some sort of an elastic sample buffer"


This is a link a friend gave me for "easy understanding" tongue.gif

Sorry i don´t get it for explanation ???

Wombat
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crazyboy_T
post Jul 26 2002, 01:19
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If you put the clock source on the external DAC you could eliminate jitter (almost) completely without any buffering. There are several disadvantages, though:
- needs a sound card that can sync to an external clock source on its spdif input
- DAC needs to have an spdif output to transmit the clock
- must change clock/divider manually on DAC for multiple sample rate support
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KikeG
post Jul 26 2002, 01:36
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QUOTE
Originally posted by Pio2001
Is it it, or am I completely confused


I guess it's something like that, I find it difficult to understand precisely, too.
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godzilla525
post Jul 26 2002, 03:00
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A stand-alone sample rate convertor with good specs... too bad soundcard manufacturers don't use it.

I'm not sure what logic the NTSC used to determine 59.94 Hz (44056 kHz). Did they have a reason for doing that or were they just high and drunk? rolleyes.gif

I also think that in a professional recording environment, if a device does not have a clock sync input then it should be avoided, but there are still some cases where this device might be needed, though I'd prefer to bypass it as opposed to being forced to route through it.

That's a nice DAC project, BTW. smile.gif


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Pio2001
post Jul 26 2002, 11:50
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QUOTE
Originally posted by Wombat
most important seems this FIFO Buffering


Don't most DACs already use it ?

I think the most important is this part :

The AD1890 and AD1891 SamplePorts include a circuit block which computes this relationship as a frequency ratio. This block employs a digital servo control system such that this ratio is not an instantaneous measurement [Unlike in the SB Live, which must behave in "samples on demand" mode, like in my picture], but rather a digitally filtered ratio. The effect of this low-pass filtering mechanism is to greatly reduce any jitter which may be present on the input or output sample clocks. [By storing the detected input sample rate in memory and keeping using it for calculatuions when it begins to jitter, exept if it jitters during more than 333 ms (3 Hz)]

QUOTE
Originally posted by crazyboy_T
If you put the clock source on the external DAC you could eliminate jitter (almost) completely without any buffering.  There are several disadvantages, though:
- needs a sound card that can sync to an external clock source on its spdif input
- DAC needs to have an spdif output to transmit the clock
- must change clock/divider manually on DAC for multiple sample rate support


Too bad ! I fullfill points 1 and 2 (using a Marian Marc 2 soundcard and a Sony DTC 55ES deck), but I can't select the sample rate of the DAC : it only works in slave mode crying.gif

BTW, their behaviour when I slave them to each other is quite funny (but don't try this at home, it may damage them).
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2Bdecided
post Jul 26 2002, 12:20
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The thing about asynchronous sample rate conversion is that the box HAS to try to remove as much jitter as possible, otherwise the jitter can get recorded into the digital signal (i.e. into the stored amplitude levels, not just the timing clock)

Whereas with synchronous sample rate conversion, the jitter doesn't matter at all. It will never effect the actual data, just the clocking of it.

The clocking can be fixed later - the data itself can't.

D.
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Wombat
post Jul 26 2002, 12:42
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Here are some thoughts and links:

http://www.diyaudio.com/forums/showthread....ght=jitter+asrc



Wombat
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KikeG
post Jul 26 2002, 13:39
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I think that the case of AD1890 and AD1891 SamplePorts is not what can be found at consumer audio, because it seems that these devices are prepared to accept data that has not a fixed clock, which is not the case for standard consumer audio, even for many pro audio. With fixed clocks the process should be easier.

It seems that most DAC's use PLL's and FIFO's to reduce jitter from the recovered clock.

About the reclocking issue we discussed at another thread, it seems that only a couple of companies make some expensive consumer DACs that actually eliminate all incoming jitter by reclocking the data with their internal clock.
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Wombat
post Jul 26 2002, 14:25
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QUOTE
I think that the case of AD1890 and AD1891 SamplePorts is not what can be found at consumer audio


They are for sure in audio products, upper class.
Also Sony is building their own Resample chips for devices like my DAC and others but
you won´t find a datasheet. Only some diagramms.

Wombat
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