IPB

Welcome Guest ( Log In | Register )

integer multiplications on IA32 architecture.
wkwai
post Aug 6 2003, 14:24
Post #1


MPEG4 AAC developer


Group: Developer
Posts: 398
Joined: 1-June 03
Member No.: 6943



Hi,


I am used to working with Assembly Language Programming on the Pentium processor generation( 166 - 200 Mhz MMX). I noticed that for operations like int16 and int32 multiplications / divisions, it used to take as long as 20 clock cycles to complete the an instruction execution. However I noticed that on a Celeron processor, (using the VTune 7.0 evaluation kit from Intel's website) it takes on 1 clock cycle to execute.. Could anyone verify this? In the past, we would use a combination of shift and add operations to implement integer multiplications / divisions.


wkwai
Go to the top of the page
+Quote Post
 
Start new topic
Replies
CiTay
post Aug 17 2003, 01:03
Post #2


Administrator


Group: Admin
Posts: 2378
Joined: 22-September 01
Member No.: 3



QUOTE (Audible! @ Aug 17 2003, 12:23 AM)
Starting at the 533MHz clock rate (and going to about 1.4GHz), the Celerons were PIII's architecture with less L2 cache, meaning SSE (1 not 2).

To make things completely confusing, there were two types of PIII Celerons, the Coppermine- and the Tualatin-based ones.

You can see the various models on this roadmap, including some future CPUs up to Q4/2004... biggrin.gif
Go to the top of the page
+Quote Post

Posts in this topic


Reply to this topicStart new topic
1 User(s) are reading this topic (1 Guests and 0 Anonymous Users)
0 Members:

 



RSS Lo-Fi Version Time is now: 18th September 2014 - 10:17