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integer multiplications on IA32 architecture.
post Aug 6 2003, 14:24
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I am used to working with Assembly Language Programming on the Pentium processor generation( 166 - 200 Mhz MMX). I noticed that for operations like int16 and int32 multiplications / divisions, it used to take as long as 20 clock cycles to complete the an instruction execution. However I noticed that on a Celeron processor, (using the VTune 7.0 evaluation kit from Intel's website) it takes on 1 clock cycle to execute.. Could anyone verify this? In the past, we would use a combination of shift and add operations to implement integer multiplications / divisions.

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post Aug 17 2003, 01:03
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QUOTE (Audible! @ Aug 17 2003, 12:23 AM)
Starting at the 533MHz clock rate (and going to about 1.4GHz), the Celerons were PIII's architecture with less L2 cache, meaning SSE (1 not 2).

To make things completely confusing, there were two types of PIII Celerons, the Coppermine- and the Tualatin-based ones.

You can see the various models on this roadmap, including some future CPUs up to Q4/2004... biggrin.gif
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