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integer multiplications on IA32 architecture.
wkwai
post Aug 6 2003, 14:24
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Hi,


I am used to working with Assembly Language Programming on the Pentium processor generation( 166 - 200 Mhz MMX). I noticed that for operations like int16 and int32 multiplications / divisions, it used to take as long as 20 clock cycles to complete the an instruction execution. However I noticed that on a Celeron processor, (using the VTune 7.0 evaluation kit from Intel's website) it takes on 1 clock cycle to execute.. Could anyone verify this? In the past, we would use a combination of shift and add operations to implement integer multiplications / divisions.


wkwai
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NumLOCK
post Aug 10 2003, 11:23
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[quote=wkwai,Aug 10 2003, 07:45 AM] I think those instructions does not exists for the Celeron and PII systems. For PIII and above, the MMX instructions actually work on 128 bit registers. That is what I noticed from the latest Intel Programmers guide.
[/quote]
They don't really exist, I was joking about their habit for strange mnemonics.

I think the 128-bit version would be best called "MMX2".

[QUOTE]I wondered how much performance gain does a 64 bit processor has over the IA32 architecture? It seems to me that most of the internal floating point operations of the IA32 architecture are already at 64 bit operations??? blink.gif [/QUOTE]
You're right, there would be little performance gain switching to 64 bits. The real advantage is the addressing.

For x86, much more useful changes would be:
- an extension to raise number of registers (8 regs is ridiculous)a 64 bit processor has over the IA32 architecture? It seems to me that most of the internal floating point operations of the IA32 architecture are already at 64 bit operations??? blink.gif [/QUOTE]
You're right, there would be little performance gain switching to 64 bits. The real advantage is the addressing.

For x86, much more useful changes would be:
- an extension to raise number of registers (8 regs is ridiculous)
- the possibility to use 3-operand instructions, like on most sane architectures (ie: ADDL source1, source2, destination).

[QUOTE]When using a floating point instructions in IA32, such as fmul, would the instructions load in the data 32 bits at a time or 64 bits? blink.gif[/QUOTE]Since most instructions see memory through 32-byte cache lines, the load will be done in one clock (assuming your 64-bit operand is duly a
- the possibility to use 3-operand instructions, like on most sane architectures (ie: ADDL source1, source2, destination).

[QUOTE]When using a floating point instructions in IA32, such as fmul, would the instructions load in the data 32 bits at a time or 64 bits? blink.gif[/QUOTE]Since most instructions see memory through 32-byte cache lines, the load will be done in one clock (assuming your 64-bit operand is duly aligned).


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