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integer multiplications on IA32 architecture.
wkwai
post Aug 6 2003, 14:24
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MPEG4 AAC developer


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Hi,


I am used to working with Assembly Language Programming on the Pentium processor generation( 166 - 200 Mhz MMX). I noticed that for operations like int16 and int32 multiplications / divisions, it used to take as long as 20 clock cycles to complete the an instruction execution. However I noticed that on a Celeron processor, (using the VTune 7.0 evaluation kit from Intel's website) it takes on 1 clock cycle to execute.. Could anyone verify this? In the past, we would use a combination of shift and add operations to implement integer multiplications / divisions.


wkwai
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wkwai
post Aug 10 2003, 07:45
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MPEG4 AAC developer


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Member No.: 6943



QUOTE (NumLOCK @ Aug 8 2003, 07:23 AM)
By the way, I loved their funny PCKUNMLL and PSKCNNNLXGLCBB mnemonics  blink.gif


I think those instructions does not exists for the Celeron and PII systems. For PIII and above, the MMX instructions actually work on 128 bit registers. That is what I noticed from the latest Intel Programmers guide.

I wondered how much performance gain does a 64 bit processor has over the IA32 architecture? It seems to me that most of the internal floating point operations of the IA32 architecture are already at 64 bit operations??? blink.gif

When using a floating point instructions in IA32, such as fmul, would the instructions load in the data 32 bits at a time or 64 bits? blink.gif
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