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integer multiplications on IA32 architecture.
wkwai
post Aug 6 2003, 14:24
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Hi,


I am used to working with Assembly Language Programming on the Pentium processor generation( 166 - 200 Mhz MMX). I noticed that for operations like int16 and int32 multiplications / divisions, it used to take as long as 20 clock cycles to complete the an instruction execution. However I noticed that on a Celeron processor, (using the VTune 7.0 evaluation kit from Intel's website) it takes on 1 clock cycle to execute.. Could anyone verify this? In the past, we would use a combination of shift and add operations to implement integer multiplications / divisions.


wkwai
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NumLOCK
post Aug 8 2003, 16:23
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QUOTE (wkwai @ Aug 8 2003, 11:25 AM)
I think so, in fact there are also penalties in mixing type bytes and int16 with int32 instructions in old Pentium processors.  In fact by using the MMX instructions for integer multiplications, the speed up time is about 100 factors. 

However on a Celeron system, MMX multiplication instructions only speed things up by about a factor of 4 only.
I think the Celeron, Pentium II and Pentium III are all based on a different architecture. 

wkwai

I think it's too bad that MMX doesn't support 32-bit multiplications.
Also the inability for MMX instructions to interoperate with x86 registers is a big design flaw in their architecture. If you want to mix both types of instructions, you have to use useless "MOVD" instructions which prevent many opportunities to optimize.

Have you seen how well Motorola's Altivec is designed, for instance ? You can do several 64x64bit multiplies in parallel...

Well after all, Intel is Intel... and stays Intel rolleyes.gif

Edit: To be completely impartial (laugh.gif), I must admit that MMX still proved useful for me, in several 24-bit graphics routines.

By the way, I loved their funny PCKUNMLL and PSKCNNNLXGLCBB mnemonics blink.gif

This post has been edited by NumLOCK: Aug 8 2003, 16:34


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